The present invention relates to integrated circuits, and to the provision of the load elements in integrated circuits. More particularly, the present invention relates to low-power integrated circuits, and to low-power static RAM access memories (SRAM's).
In integrated circuits generally, it is necessary to be able to change the voltages of nodes in two directions. For example, in conventional CMOS logic, p-channel insulated gate field effect transistors (PMOS devices) are used to pull up the voltage of a node, and NMOS devices are used to pull down the voltage of a node. In conventional NMOS logic, NMOS devices are used to pull down nodes, and resistor loads are used to pull up the nodes.
A specific example of this is in SRAMs (static random access memories). In a conventional CMOS SRAM, six transistors are used in each cell. The cell has two data nodes, which have opposite logic states. Each node is connected to ground through an NMOS driver transistor. The driver transisitor which connects each node to ground has its gate connected to the opposite data node so that, when one data node goes high, it will pull the opposite data load low by turning on its driver transistor. Similarly, each node is connected, through a PMOS pull-up transistor, to the high supply voltage V.sub.DD (which is typically 5 volts). Again, the data nodes are connected to control the pull-up transistors of the opposite data node, so that, when one of the data nodes goes low, it will turn on the pull up transistor of the opposite node, so that the opposite node is held high. In addition, two pass transistors (normally NMOS transistors) selectively connect the two data nodes to a pair of bit lines. (The gates of the pass transistors are connected to a word line, so that the cell nodes will be connected to the bit line pair only if the word line goes high.) Such a 6-transistor cell will hold its logic state indefinitely (as long as the supply voltages are maintained and no transient upset occurs). Moreover, while such a cell is simply holding data, it has almost zero power consumption, since each of the nodes will be disconnected from one of the two power supply voltages.
The low power consumption of CMOS is extremely advantageous in a wide variety of environments, and is one of the reasons why CMOS logic has become very widely used for a wide variety of digital circuits. Low power consumption is not only advantageous where the total drain on system power supply must be conserved (as, for example, in applications where the power is being supplied from a battery), but also implies that the on-chip power dissipation will be less. This can be important in a wide variety of applications where a very high density is required.
However, while conventional CMOS logic has some major advantages, it also has significant disadvantages. The use of both PMOS and NMOS devices means that additional masking and doping steps must be used to provide both n-type device areas (for the PMOS devices) and p-type device areas (for the NMOS active devices). Moreover, for a given device area, the use of both PMOS and NMOS active devices means that some new spacing constraints must be observed. An important spacing constraint is imposed by the need to avoid latchup.
Latchup is a failure mode to which conventional bulk CMOS devices are inherently susceptible. A parasitic thyristor exists wherever an N+ source/drain region in the p- well of an NMOS device is close to a P+ source/drain region in the n- well of a PMOS device. The N+ source/drain, the P-well, the N-well, and the P+ source/drain of the PMOS device define a PNPN parasitic thyristor structure. In many locations, an n+ region will be connected to the positive power supply V.sub.DD and the nearest p+ will be connected to ground. Thus, if the parasitic thyristor fires, it can conduct a large amount of current. This can provide a stuck logic state, or even destroy the device.
An immense amount of effort has been devoted to reducing the propensity of CMOS devices to latchup, and some CMOS process produce devices with reduced susceptibility to latchup. However, for any conventional bulk CMOS process, a certain minimum P+ to N+ separation must be observed, to prevent the possibility of latchup.
Thus, an inherent limitation of conventional CMOS technology is that some space is lost at the interface between PMOS and NMOS active device regions. This constraint is particularly inconvenient in memory design. In the conventional 6-transistor CMOS SRAM cell described above, the transistor types require that a P-well/N-well boundary must run through every single memory cell in the array.
NMOS static random access memory cells tend to be more compact than PMOS static random access memory cells, because they do not require a P-well/N-well boundary within the cell. However, the static power consumption of NMOS memory cells is much larger than for CMOS memory cells. This is because current will flow through at least one of the load resistors all the time.
During normal operating conditions, the current provided by the load resistors only needs to be large enough to compensate for junction leakage. With normal high-quality processing techniques, this junction leakage will be substantially less than a picoAmpere per cell, and may range down to values in the neighborhood of one femtoAmpere (10.sup.-15 Ampere) per cell. The highest-resistivity material conventionally available in integrated circuit processing is intrinsic polysilicon. While this material has very high bulk resitivity, it is difficult to fabricate it with a sheet resistance higher than a few hundred gigohms per square. This means that the largest resistor value which can be conveniently placed within a memory cell layout (without expanding the cell) will be about one teraohm. A one-teraohm resistor will pass a current, at 5 Volts, of 5 picoamps. Therefore, this resistor value is still several times smaller than would be desirable for low-power applications.
Other attempts to make compact high-value resistors have used oxygen implantation into polysilicon. However, such process approaches require the use of quite unusual process steps.
The present invention provides a novel load element for integrated circuits. This load element is a very high-impedance compact vertical resistance. This resistance readily provides a very compact load element, which can provide a sub picoAmpere current.
A further advantageous teaching of the present application is a novel SRAM cell, wherein very -high-impedance doped oxide load elements are used to provide a 4-transistor SRAM cell with very low standby current (less than a picoAmpere). Thus, this cell provides extremely high power efficiency, while also providing compact layout.
A particular advantage of this doped-oxide resistance element is that its temperature dependence closely tracks the temperature dependence of the junction leakage in the integrated circuit. Thus, areas can be selected so that the current passed by the load elements is greater than the leakage current at every operating temperature, but the current passed by the load elements is small enough that battery energy is well conserved. (Minimization of load current is driven by the demands of battery lifetime. As long as the specification for battery lifetime can be met, increased pull-up current will help the electrical operation of the cell). The static power consumption of a full-CMOS device (six-transistor cell) will be defined by the leakage current in any case, so it may be seen that the SRAM provided by the present invention can actually achieve power dissipation levels which are reasonably close to those of a full-CMOS SRAM using 6-transistor cells.
The innovative load used in the SRAM of the present invention will not be slower than an analogous six-transistor cell. In fact, if desired, some of the area savings provided by the compact load element can be used to enlarge the driver and pass transistors, so that an SRAM according to the present invention can be made faster than a full-CMOS SRAM of comparable dimensions and technology.
A further advantage of the SRAM of the present invention is that it can be compactly laid out in a single-polysilicon, single-metal configuration. This means that fabrication costs can be drastically reduced over the double-polysilicon and double-metal technologies commonly used. This in turn means that yield can be increased. While this configuration is somewhat slower than embodiments using double-level metal, its advantages may make it preferable for some applications.
Note also that the fabrication process is much simpler than that of conventional DRAM processing. DRAM processing normally requires the use of charge pumps and (at the 1M (one megabit) level and above) of trench processing. Thus, DRAM process development has increasingly diverged from the processing used for general-purpose digital circuits. This process divergence has contributed to the high cost of entry into the DRAM manufacturing business. By contrast, the SRAM provided by the innovative teachings herein is not only compatible with standard logic processing (requiring only one additional masking and implantation step), but can actually be made simpler than standard logic processing (since functional and compact SRAMs can be made with a single-poly single-metal process). This means that, by using the innovative teachings set forth herein, companies wishing to manufacture low-cost memory can easily begin to manufacture SRAMs.
The lowest-cost (mass-market) SRAMs have typically had access times which are less than those of the fastest mass-market DRAMs by about 30-50%. The increasing speeds of advanced commercial microprocessors have made this access time more relevant, since (for example) a 20 MHz microprocessor can typically access a 40 nsec SRAM in one cycle of the processor's internal clock, but an 85 nsec DRAM will require at least tow clock cycles. Moreover, SRAMs are much more convenient for system designers, because they do not require refreshing. However, even the lowest-cost SRAM chips have normally had a substantially higher cost per bit than DRAMs.
A recent trend in the design of small computers (such as those built around an 80386 microprocessor) has been to use SRAM rather than DRAM chips for main memory. Notwithstanding the high cost of SRAMs, their advantages have led to such use in high-end personal computers. Thus, the SRAM described herein may also be particularly advantageous for applications where SRAMs are competing with DRAMs for system design. The present invention provides a cost-per-bit which is much lower than that of the traditional SRAM process, and much closer to that of a DRAM.
Of course, memory cells do not have to be used only in memory parts. Microprocessors (and other complex logic parts) commonly contain substantial quantities of memory. The present invention provides a very low-power compact memory array, and blocks of memory of this kind can readily be inserted into the design of a complex logic part. A particular advantage of the disclosed single-poly, single metal layout is that the space over this memory cell can readily be used, in complex logic parts, for routing lines in second-level metal. Similarly, in triple-poly processes, it may be possible to route lines in third poly right over the memory array.
The innovative load element described herein can also be used in non-memory circuits in a wide variety of other integrated circuit devices, including analog integrated circuits and various random-logic digital circuits.
Preferably this improved high-impedance load device is used in combination with a full CMOS process. This means that the compact load can be used in locations where high pull-up current is not necessary, and PMOS active devices can be used in other locations. For example, in the SRAM provided by the presently preferred embodiment, the peripheral logic is full-CMOS, i.e. uses PMOS active devices for pull-up (e.g. for bit line precharge and in buffers).
The present invention also disclosed a novel method for fabricating doped-oxide loads of this type. In this novel method, a polysilicon capping level is deposited over the oxide before it is implanted. This capping level of polysilicon means that the implant energy can be selected so that the peak of the implant falls in the middle of the oxide, and yet the peak of the implant distribution is a fairly broad peak. (This is, the straggle of the implant is caused to be reasonably high.) Thus, sharp gradients in conductivity do not occur within the small thickness of the oxide.
Another novel teaching of the present application is that a gate oxide is preferably used for the doped oxide conductor. This gate oxide is formed, using methods well known to those in the MOS art, to have a very high purity and high quality microstructure. This means that the qualities of this oxide can be very closely controlled. In alternative embodiments, an oxide over polysilicon can be used to provide a poly-to-poly resistor, but this is less preferable.
The use of gate oxide and a polysilicon capping layer has the further advantage that the tail of the implant which dopes the oxide will also dope the substrate. This assures a low contact resistance between the resistor and the substrate.
An SRAM cell which has such a high-impedance load may be more susceptible to single event upset than a 6-transistor CMOS SRAM cell. However, the SRAM provided by the present invention will be no worse in this respect than a conventional DRAM cell.
Single-event upset is normally caused when a particle of ionizing radiation (for example, an alpha particle) is absorbed by the integrated circuit. As the particle passes through the substrate, it will generate a flow of electron-hole pairs. These carriers will diffuse to all parts of the integrated circuit, so that logic states which are stored as charged packets in the substrate will be lost.
The SRAM cell provided by the present invention has dimensions which are more than 40% smaller than a 6-transistor full-CMOS SRAM cell, for comparable device dimensions. The precise area savings will, of course, depend on the particular process and layout optimization being used, but a substantial area savings is available in any process.
A further advantage of the disclosed SRAM cell, and of the disclosed load element, is that the scaling is extremely favorable. As is well known to those in the integrated circuit art, the minimum dimensions of devices in mass production have been continually reduced, over a period of years, to achieve lower cost and greater functionality. To adapt existing device designs to reduced manufacturing dimensions, direct linear shrinkage is typically used. This process is known as "scaling". For example, one a process has been shown to be reliable, manufacturers may attempt to implement an "80% shrink," where all lateral dimensions in the device layout are simply multiplied by 0.8.
Although linear scaling is the ideal case, adjustments must be made in practice. For example, scaling of the vertical dimensions must often be adjusted. As lateral dimensions shrink, vertical dimensions (such as the depth of the source/drain junctions, the thickness of the gate oxide and thick field-isolation oxides, and the thicknesses of deposited layers) are normally also reduced, but this reduction is often not proportional to the lateral shrinkage. For example, the minimum thickness of the gate oxide will be limited by leakage and breakdown characteristics. Many device characteristics do not scale favorably to smaller dimensions. For example, metal lines tend to become slower: the resistance (per unit length) of a metal line scales approximately as the square of the scaling parameter, but its capacitance (per unit length) scales with an exponent which is slightly less that one (due to fringing field effects). Thus, an important criteria in selecting process features is scaling, since it is desirable not to design in a process feature which will soon have to be designed out again.
The present invention is particularly advantageous in its scaling behavior. The specific resistance of the vertical resistors provided is so high that one minimum-area (lambda.sup.2) contact provides a current equal to the leakage current generated by active devices over an area of about one hundred to one thousand lambda.sup.2. As the minimum dimension lambda is scaled, the area of the resistor will naturally scale in approximate proportion to the area of the circuit, and therefore the load current will track the leakage current over a wide scaling range.
Of course, if a higher or lower area-specific resistance (ohm-cm.sup.2) is desired, the implantation dose may be changed. At higher doses the innovative load element exhibits a more linear relation of I to V. (At the doses used in the presently preferred embodiment, the disclosed load element has electrical characteristics which are rather nonlinear, as discussed below.)
A further advantage of the disclosed innovative process is that it does not introduce critical process steps, but merely takes advantage of an existing critical process step. Gate oxide growth is very critical in MOS processing, and a tremendous amount of engineering has been invested to achieve reliable processes for manufacturing thin gate oxide layers with very high quality and very low defects. The disclosed innovative load takes advantage of this engineering, and of the presence of these steps in a normal MOS process flow, to provide a new functionality without requiring additional process controls or any significant yield degradation.
A further novel and advantageous teaching is that high-impedance resistors, according to the present invention, can be combined with V.sub.DD power supply routing through a substrate diffusion. By routing power supply through a substrate diffusion, the high-impedance oxide resistors can be provided at the surface of this diffusion, where polysilicon lines make connection from the power supply voltage to the cell nodes. The load elements provided by the present invention are essentially no larger than the area which would be required for this contact any way, so that it may be seen that the area of the SRAM cell provided by the present invention is almost as small as that which would be required for a 4-transistor SRAM cell with no load element whatsoever (if such a thing were possible).
A further novel teaching provided by the present invention is an integrated circuit wherein a chain of high-impedance load elements as disclosed is used as a resistive divider network, to provide a high-impedance fully static reference voltage at a desired fraction of the supply voltage V.sub.DD. Such a reference voltage is highly advantageous in many applications, since higher-power negative-feedback circuits can be turned on, when needed, to provide a low impedance output which tracks this high-impedance reference voltage.
In the presently preferred embodiment, the peripheral logic (which includes such conventional elements as address decoders, word line drivers, sense amplifiers, output buffers, write buffers, etc.) is full CMOS. Thus, PMOS devices are used to pull up the bit lines for pre-charge, although only passive load elements are used for pull-up in the cells.
A similar technique of combining high-impedance and low-impedance pull-ups can be used in random logic. Where it is simply necessary to maintain a node in a high state, or to assure that a node is not in an unknown state after having been inactive for some time, high-impedance load elements can advantageously be used. Where rapid low-to-high transitions are needed, PMOS pull-up devices would be used. For example, such a high-impedance load element could be used with a one-shot circuit which pulled up a node when a low-to-high transition was needed. For another example, such a high-impedance load can be used in open drain circuits, e.g. for wired-OR logic.
Another sample use of the high-impedance load to the present application is a a latching feedback element in logic circuits. For example, where two inverters are in series, the output of the second inverter could be fed back through a high-impedance load to the input of the first inverter. Since the load is so high-impedance, this load would not significantly retard the time required to switch the input to the first impedance. However, this feedback could provide enough current to maintain the first inverter in a known and stable state, until some other upstream active logic element applied a current to switch the first inverter.